1. Field of the Invention
The present invention relates to an electronic circuit that is capable of suitably carrying out communications between substrates such as IC (Integrated Circuit) bare chips, and PCBs (Printed Circuit Boards).
2. Description of the Related Art
Downsizing and high performance have been further advanced in recent electronic devices. In line therewith, incorporated LSIs (Large Scale Integration) have been downsized and high speed processing has progressed. As means for achieving downsizing and high-speed processing, it is desirable that entire functions are included in one package, and now generally two types of realization methods exist.
As the first method, a system called “system on chip (SoC)” is available, which incorporates the entire system on a single bare chip. This system is made expensive because different process technologies are realized on one bare chip, and the yield thereof is lowered due to an increase in the chip area.
As the second method, a system called “system in package (SiP)” is available, which seals a plurality of bare chips in one package. With this technique, it is expected that separate chips realize functions produced through different processes, wherein the yield per bare chip is increased, and production costs can be made inexpensive. However, since it becomes necessary that different chips are interconnected to each other, three types of connection techniques exist.
The first method for interconnection in SiP is a method conventionally using wire bonding. In this case, the number of connections between chips is the same as in a conventional package or less, wherein a problem occurs in the communications bandwidth. In addition, three-dimensional mounting is indispensable when reducing the mounting area, wherein since, in the wire bonding system, it is necessary to make chips smaller that are to be stacked up, it is difficult to form a bus because the mounting area is restricted and major connections are based on one-to-one connection.
The second method for interconnection in SiP is a method by which chips are three-dimensionally mounted, and connections are based on micro bumps. In this method, costs up to face-to-face mounting of two chips are inexpensive. However, as regards mounting of three or more chips, it is necessary to physically produce a communications path passing through a chip itself or a build-up substrate, a so-called “through hole,” wherein an exclusive process technology and highly precise processing accuracy are demanded: resulting in an increase in production costs.
The third method for interconnection in SiP is a method for three-dimensionally mounting chips and electrically connecting chips by means of capacitive coupling. Although, for face-to-face mounting up to two chips, costs thereof are inexpensive and high-speed communications are possible, transmission efficiency of signals is radically worsened in three or more chips, wherein power consumption is increased.
For this reason, it is proposed that communications between chips are carried out by means of an antenna (for example, refer to Patent Document 1).
[Patent Document 1] Japanese Unexamined Patent Application Publication No. H11-68033
However, even in the case of using an antenna, where signals are attempted to be transmitted over chips with three or more chips mounted, it is necessary that an electric field generated by the antenna passes through a number of substances whose dielectric constants are different from each other (biased silicon substrate, doped silicon, oxide film, nitride film, etc.), wherein reflection is generated at a boundary phase, resulting in a worsening in transmission efficiency.
In view of the above-described problems, it is therefore an object of the present invention to provide an electronic circuit capable of efficiently transmitting signals even in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. The substrates include an IC bare chip and a PCB.